1. Field of the Invention
The invention relates to integrated circuits and more particularly to a method of fabricating polysilicon resistors to improve resistance mismatch between the polysilicon resistors in an integrated circuit and an integrated circuit fabricated by the method.
2. Description of the Related Art
Integrated circuits are manufactured using a wide variety of well-known techniques. In the manufacturing of integrated circuits, active and passive components are formed on a semiconductor substrate such as a silicon wafer, and then interconnected in a desired manner.
Resistors are typically formed in a semiconductor substrate using one or two well-known techniques. In the first technique, regions of the semiconductor substrate are doped with n-type or p-type dopants. This provides conductive regions in the semiconductor substrate having a desired resistivity. By forming ohmic contacts to a pair of spaced-apart locations in the conductive regions, a diffused region is provided. Such resistors are referred to as diffused resistors.
In the second technique, an insulator layer, i.e. dielectric layer, is formed on the surface of a semiconductor substrate. Next, a layer of polysilicon is formed on the insulator layer. The polysilicon layer is doped with n-type or p-type dopant. The dopants form a conductive region having a desired resistivity. Next, ohmic connections are formed on a pair of spaced-apart regions on the polysilicon layer to complete the resistor. The resistors are referred to as polysilicon resistors.
Integrated circuit fabricating processes include annealing operations to perform various function, including activation of dopants and reduction of crystal lattice damage from ion implantation. Laser scan annealing is an annealing technique that has advantages over other annealing techniques, such as conventional rapid thermal annealing, flash annealing or furnace annealing, which is used in old process node, such as the 100 nm node. Laser scan annealing is being used more frequently in advanced process nodes, such as a 65 nm node and beyond. However, defect mechanisms unique to laser scan annealing have been observed.